Improving Logic Optimization in Sequential Circuits using Majority-inverter Graphs

Majority-inverter graph (MIG) is a recently introduced Boolean network that enables efficient logic manipulation. Recent works show that MIGs are capable of achieving significant improvements in area, delay, and power when comparing to current academic and commercial tools. However, current MIG optimizations are limited to combinational circuits, missing the sequential elements which are ubiquitous in practical implementations. This paper is the first to study the sequential optimization opportunities using MIGs. The presented extension leverages the efficiency of MIGs area and depth-oriented rewriting algorithms for combinational circuits in sequential networks. Experimental results showed that, averaged over the OpenCores benchmark suite, (1) when considering technology-independent evaluations, compared to a popular academic tool, our MIG-based sequential optimization brings an improvement of 9% and 38% in area and delay respectively; (2) when using a standard optimization+technology mapping flow for ASICs with a 7nm predictive standard cell library, the proposed sequential optimizer outperforms both academic and commercial tools in energy-delay product (EDP) by 12% and 4% respectively and area-delay product (ADP) by 13% and 7% respectively.