A 1.25Gbps FPGA I/O Cell Design for Source-Synchronous System in 65nm CMOS Process

In this paper, a field programmable gate array (FPGA) I/O cell developed to support 1.25 gigabits-per-second source-synchronous standard is presented. The I/O cell provides the compatibility of 38 high-speed I/O standards, features wide supply voltage range, 3.3V voltage tolerance. To achieve the speed and performance, a build-in serializer de-serializer (SERDES) and a DLL-compensated delay chain are introduced into the I/O cell. The proposed I/O cell has been fabricated and integrated in an SRAM-based FPGA with commercial 65nm CMOS process.