A Level Crossing ADC with Variable Symtem Hysteresis

This paper proposes a 6 bit floating window asynchronous level crossing ADC in 180nm CMOS technology for applications with sparse input signals. Two different hysteresis comparators are used to detect the rise and fall of the input signals respectively. The hysteresis width can changing with the change speed of input signal, so that the level crossing ADC can not only reduce the collection of invalid data when the signal changes slowly, but also collect the peak signal when the signal changes rapidly. Operating under a supply voltage of 1.8 V, the ADC consumes 31.8-41.5 μnW from 1 Hz to 50 kHz.