High-temperature latchup characteristics in VLSI CMOS circuits

A simple worst-case analytical model of holding currents and an empirical model of trigger currents are reported and shown to agree with experimental measurements in the range of 25-225 degrees C. Whereas standard bulk CMOS inverters and ring oscillators are invariably found to latchup near 125 degrees C, their counterparts built on epitaxial wafers remain latchup free up to at least 250 degrees C. These results add to an ongoing systematic effort to model high-temperature effects in integrated MOS technologies and provide worst case latchup information in the commercial temperature range and beyond.<>