Low Power Physical Design and Verification in 16nm FinFET Technology

In the recent years, there has been rapid increase in complexity of System on Chip designs. As the functionality of the chip increases, design and verification runtime also increases. Physical design involves both design and verification of the layout. Thus major challenge for semiconductor industries is that the design of chip and its verification has to be done efficiently keeping in mind the stringent tape out schedule. Power consumption is of primary concern in the semiconductor industry as the power consumed by the chip directly affects the chip's performance and lifetime. Specifically for sub nanometer technologies, leakage power consumption is dominant. Thus there is a need for reduction in leakage power consumption by implementation of appropriate power gating techniques in the design flow. In the proposed design flow, using multi threshold cells, this has been addressed and a novel low power design is implemented using 16nm FinFET technology through power switches in the power domain. For design implementation various tools such as Innovus, IC Compiler II and Calibre Design RVE is used in this paper.