Area Efficient Architecture for high speed wide data adders in Xilinx FPGAs

Modern FPGA families have inbuilt, fast and dedicated carry chain logic embedded in the configurable logic blocks which improves the performance of adder circuitry. In this paper we propose a fast and area efficient adder for Xilinx FPGA families by efficiently utilizing the 6-input LUTs and inbuilt dedicated carry logic chain. The proposed adder is implemented by splitting the N-bit adder into three sections where the first section consists of K/2 carry compression (cc) cells which calculates the carry of K least significant bits and this carry out is given as the carry input to calculate the sum of M most significant bits. The second section consists of K/2 sum-out (so) cells which calculates the sum of k least significant bits and the third section consists of M carry select adder (csa) cells instead of M ripple carry adder for calculating the sum of M most significant bits which in turn reduces the delay without any increase in area. The result shows that the proposed adder architecture with carry select adder and carry chain is faster than the one with normal ripple carry adder without any area overhead. The proposed N-bit adder improves the delay by about 16% (32-bit) to 29% (128-bit) compared to the state-of-the-art N-bit adder [8] and a normal adder respectively.