High Speed Memory Cell with Data Integrity in QCA

The design issues in CMOS at Nano meter levels has increased the demand for post-CMOS technologies. Quantum-dot Cellular automata is one of the promising post-CMOS technology that can be used in the near future. It is a transistor-less nanotechnology paradigm that has the competence to design high speed and low power Nanoscale circuits with higher packaging densities. Data integrity is a key factor in the design of any memory storage device. In this paper, a novel memory cell architecture is proposed in QCA. The proposed design has more data integrity compared to the existing designs. Simulation results shows that the proposed design has higher speed compared to the existing designs. The proposed memory cell can be extended to implement any large size memory circuit in QCA. QCADesigner 2.0.3 is used for the validation of the proposed design in QCA.