Review on LFSR for Low Power BIST

While testing an integrated circuit, large chip size, and excess power dissipation are the major issues. As compared to its working mode, the testing mode power dissipation is very high. In addition to this, the inefficiency of ATE and its time-consuming nature makes the external testing much more difficult. LFSR is used for testing ASIC chips. The pseudo-random variable generated by the LFSR is used for the testing process. The pseudo-random variable testing has some advantages such that it uses simple hardware for the on-chip test generating process. BIST is one of the most efficient low power testing methods. LFSR is used in the BIST for the generation of test patterns. This paper compares the various architecture of the LFSR for BIST and its associated power dissipation.