Analysis and Design of CD-Cell-Based Fifth-Order Boost Converter With Robust Stability Considerations

The reported fifth-order boost topologies exhibiting gain (1 + D1)/(1 - D1) find limited utility in point-of-load applications due to lack of common ground, inverted load voltage polarity, highly pulsating source current, and more switching devices. This article evolves a fifth-order boost converter that successfully overcomes the enlisted limitations. The basis for the evolution of this topology is the addition of a charge-pump capacitor with a diode to the SEPIC converter. This modification alleviates the shortcomings of the existing higher order boost topologies with identical voltage gain. A remarkable feature of this topology is reduced voltage stress on all of its intermediate capacitors. After performing extensive steady-state and state-space analysis, a detailed comparison highlighting significant features is brought out. To demonstrate the proposed converter's utility, a complex proportional-integral lead compensator (PILC) is designed by placing the closed-loop dominant poles satisfying the predefined time-domain specifications, including phase margin, to ensure sufficient stability. PILC gives the flexibility to choose the complex conjugate zeros of the lead portion making the closed-loop system exhibit better disturbance rejection features. The robustness of the designed controller is verified through performance metric computation of the contoured robust controller bode plot. The converter's salient features, the developed controller design, and its robustness against the structured uncertainties are validated experimentally on a 100-150-W prototype module.