Wafer Level Integration of Thin Silicon Bare Dies Within Flexible Label

This paper presents new developments on the integration of ultra-thin silicon bare dies within a flexible label made on wafer carrier. It is proposed to interconnect silicon die on an electrical network by flip-chip and to perform collective thinning using conventional microelectronic equipment. After dies attach, they are collectively thinned down below 100μm and encapsulated in a polymer. Finally, the flex is take off from its wafer carrier. The total thickness of the label is approximately 150μm. Test flexible labels were made on 200 mm wafer and designed in order to test electrical interconnection between thin silicon die and electrical network on flex. The test label will be fully described in this paper. A technical focus will be done on the most important process steps for the silicon die integration and electrical results of four point Kelvin and daisy chain patterns will be presented and commented.