Material and Structure Design Optimization for Panel-Level Fan-Out Packaging

In recent years, the evolution of semiconductor packages is driven by the consumer demands of Internet of Things (IoT), mobile phones, wearable devices, and tablets. Manufacturing has evolved from wafer-level chip-scale packaging (WLCSP) to fan-out wafer-level processing (FOWLP) and 2.5/3D packaging. The panel-based fan-out processing was highly noticed. It is the best solution to have both high density and cost efficiency. In this study, the warpage behavior at mold and carrier release stages of the Panel-Level Fan-Out (PLFO) device was optimized by the theoretical and simulation tools. The panel-level (300×300 mm2) warpage of the PLFO test vehicle was measured by advanced metrology analyzer (aMA), which can not only do the global measure of warpage of the full panel, but also do the local measure of the unit package. The Finite Element Method (FEM) analysis was then conducted for the corresponding test vehicle with considering the temperature dependent material properties, including Young's modulus and Coefficient Thermal Expansion (CTE), and the simulated warpage was highly correlated to the measured result for modeling validation. Four-layer and three-layer curvature theoretical formulas were developed for mold and carrier release stages, respectively, and used to predict the trends versus different factors. These trends were verified by FEM simulations. The optimal curvature was then obtained by the optimized factors.