Low-Power High-Input-Impedance EEG Signal Acquisition SoC With Fully Integrated IA and Signal-Specific ADC for Wearable Applications

This paper presents a low-power high-input-impedance analog-front-end (AFE) design including an instrumentational-amplifier (IA) and a neural-signal-specific ADC (NSS-ADC) for continuous acquisition of electroencephalography (EEG) signals. In the proposed AFE, low-voltage low-power design techniques are used to reduce the power consumption of the whole system. Furthermore, by utilizing the proposed NSS-ADC, high-amplitude EEG spikes, which convey more important information, are converted with higher resolutions, while the background-noise (B-Noise) of the EEG signal is converted with the lowest resolution. Hence, when the NSS-ADC enters the inactive region, the resolution- and DAC- controlling-units (RCU and DCU) set the analog and digital components of the NSS-ADC into off mode, which leads to power reduction. Based on measurement results, the AFE consumes a power of 3.7 μW under the sampling rate of 20 KS/s. In the proposed AFE, to avoid signal attenuation, active-electrodes (AEs) are utilized to enhance the input impedance of the AFE up to 102 GΩ and 5.2 GΩ at 1 Hz and 20 Hz, respectively. In addition, by using circuit-design techniques the input-referred-noise is reduced as low as 1.5 μVrms over 0.5-1.2 kHz. Finally, by using a transconductance-driven-right-leg (TDRL) and a common-mode-feedback (CMFB) blocks, a common-mode-rejection-ratio (CMRR) of 108 dB is achieved.