A Variability Source for Nanosheet GAA Transistors for sub-7nm Nodes

Due to the complex process flow of the Gate All Around (GAA) stacked NSFET, new forms of process variability arise which are dominant over the conventional process variability like MGG and LER. Multi- VT options in NSFET are achieved by gate metal thickness modulation, which can cause VT -variability if the process lacks precision. In this paper, we present a new form of process variability called Metal Thickness Variation (MTV) caused by inter-sheet spacing variation, compared to an `ideal NSFET'. There are currently no models available in TCAD to study the thickness dependent Work-function (WF) VT engineering. Hence, using physics based analytical model, we analyzed the variability in VT due to this new variability source. We obtained the VT distribution caused by MTV and estimated the standard deviation in VT, due to process variations and provided a way to suppress variability. Our results show that MTV emerges as a dominant source of variability and is insensitive for gate length scaling.