Clock Variation Impact on Digital Filter Performance

Applications involving embedded systems utilize digital filters for signal conditioning. Such applications proliferated over the years due to advancements of microprocessor technology and their capability to perform numerical operations at a faster rate. An algorithm implemented in a microprocessor is executed at a specific frequency derived based on the clock source provided to the device. Typically, this frequency is expected to be static and, in most applications, same as the sampling frequency of the system. Assumption of static sampling frequency is a primary design factor. Aging, manufacturing process variations, user error and environment factors tend to alter the frequency of the clock source resulting changes in the sampling frequency of the microprocessor. Such change adversely effects digital filter performance.