A Fast On-Chip SVM-Training System With Dual-Mode Configurable Pipelines and MSMO Scheduler

On-chip training of support vector machine (SVM) is limited by its low speed and large resource cost. In this paper, a novel integrated circuit implementation of the modified sequential minimal optimization (MSMO) algorithm for fast on-chip SVM training is carried out to speed up the training process of hardware systems. The dual-mode configurable pipelines with the table-driven-based Gaussian kernels are implemented to accelerate the prediction error updating process of the MSMO algorithm and to adapt to both linear and nonlinear datasets with different feature vector dimensions. Efficient MSMO scheduler is proposed to effectively control the computation and data flows of the system. The presented design is verified on a field-programmable gate array using three datasets with different feature vector dimensions. The experimental results show that the design improves the training speed and adaptability of the hardware system without excessively increasing chip area or power consumption, which facilitates the low-cost fast on-chip SVM training.