Cryptographic Coprocessor with Modular Architecture for Research and Development of Countermeasures Against Power-Based Side-Channel Attacks

In modern information processing systems, ensuring confidentiality and secure data transmission is an extremely important issue. However, even the most secure cryptographic algorithm may be insufficient, if its implementation does not take into account the threat of information leak through side-channels. Performing an attack on an unsecured device can be very simple and may not require expensive hardware. For this reason research and development of countermeasures against such attacks is very important. This paper presents an environment designed to facilitate research, development and evaluation of countermeasures protecting hardware implementation of cryptographic primitives against side-channel attacks based on power consumption analysis. The environment is composed of hardware cryptographic coprocessor with modular architecture, data transfer and configuration layers and software testbench for design verification. Different crypto primitives (block ciphers, hash functions, checksum) were implemented along with basic countermeasures. Utilized methods of power consumption approximation are also described. Evaluation of capabilities of the entire environment prove that both, hardware architecture and testbench provide easily extensible and versatile framework for research and development of countermeasures against power-based side-channel attacks.