Design and Implementation of High Speed Combined OSPI and HyperBus Flash Memory Host Controller

This paper describes a new high speed combined Octal Serial Peripheral Interface (SPI) and HyperBus flash memory host controller, which can work in a mixed single-data-rate/double-data-rate (SDR/DDR) mode. The proposed controller can support SPI, Dual/Quad/Octal SPI, and HyperBus protocols. The operation frequency ranges from 5 up to 200MHz for SDR/DDR write and read operations, which can make systems boot from flash at the low frequency and run software at the high frequency. The controller features an efficient calibration method for maximizing margin for receiving data. This memory controller prototype is designed and implemented on Xilinx Zynq-7030 Field-programmable gate array (FPGA).