Low Power Design of XOR Circuit

Anapproach of low power XOR gate is presented. Comparison has been done for traditional XOR and XOR heavysystems like binary to gray converter, parity checker. There are significant improvements in power consumption and area with cost of increaseddelay. As compared with traditional XOR gate this design consumes about 3 times less power and because of using less number of transistors area is decreased also. There is a disadvantage for this design in case of delay. It has about 30% more delay as compared with traditional XOR gate. Simulation was performed with SAED 32/28 nm technology.