Impact of trapped interface charges on short channel characteristics of WFE high-K SOI MOSFET

In the present exertion, we have developed a surface potential and threshold voltage model for linearly graded work function engineered high-K Silicon On Insulator MOSFET including interface charges trapped at both front/channel and buried oxide/channel interfaces. The analytical model is derived utilizing 2D Poisson's equation and criteria of minimum surface potential is further employed for exploring device performance in terms of potential profile, electric field distribution and threshold voltage decay. The interface trapped charges modulate the short channel characteristics of the device structure which is investigated thoroughly in this research endeavor. The same is compared ignoring the trapped charge to grab its effect on the device performance. All the analytical results show excellent concordance when matched with data of ATLAS device simulator thus validating the precision of our model.