Understanding NAND AC Timing Parameters and How to Accurately Implement them in SI Simulations

The Power Delivery Network (PDN) of the NAND Flash silicon characterization environment contributes significant jitter in NAND clock signals (DQS/BDQS) duty cycles. The specification values for the clock pulse width is used in signal integrity (SI) simulation, include both the average duty cycle distortion and the typical duty-cycle jitter. This paper identifies the gap in current SI simulation methodology and describes how to correctly implement NAND AC timing parameter specifications for more accurate system level performance prediction. Critical NAND AC timing parameters were simulated in the characterization environment, demonstrating the importance of the proposed changes.