Open Defect Detection of Through Silicon Vias for Structural Power Integrity Test of 3D-ICs

Increasing test coverage of power integrity in manufacturing test of 3D-ICs is necessary to achieve zero DPPM (Defect Parts Per Million) in the market. Although only functional tests are applied to analog circuits such as power distribution networks in general, applying structural tests will increase the coverage. This paper proposes to measure resistance between a pair of bumps under TSVs (Through Silicon Vias) to detect open defects of the TSVs as a part of structural power integrity test. Diagnostic performance of each bump pair is evaluated by simulations and the best one is selected to detect each TSV defect. Resistance threshold for the defect detection is determined considering trade-off between fault coverage and yield loss. Experimental simulations of power distribution network in a 3DIC with 2 dies are conducted and the trade-off between them is derived.