A Model-driven Approach for Formal Verification of Embedded Systems Using Timed Colored Petri Nets

The exponential use of time dependant and concurrent embedded systems in safety critical situations demands correctness of their behavior. Early design phase verification techniques allow us to ensure system's safety with minimum cost. In Model Driven Software Engineering (MDSE), Unified Modeling Language (UML) is considered as a standard way to visualize system's design but it is a semiformal language and lacks support for precise verification mechanisms to guarantee system's safety. To solve this issue, we have proposed a model driven approach to formalize timed and concurrent embedded systems using Timed Colored Petri Nets. This paper describes the rules for transformation of timed UML State Machines (source model) to Timed Colored Petri Nets (target model). We have focused on timing and behavioral aspects of concurrent embedded systems. We have also demonstrated the applicability of our approach with the help of a benchmark case study using CPN Tools.