Overview and Comparative Performance Analysis of Various Full Adder Cells in 90 nm Technology

Full Adders considered as the major component in Arithmetic Logic Unit of digital signal processing chips and microprocessors gained much interest among researchers over the years. As a result, various adder cells have been developed by employing various logic styles. Therefore, it is necessary to have a complete overview of the various sorts of full adders to Figure out their performance level. This paper presents an overview and comparative analysis of different sorts of full adder cells. Analysis and simulation on Complementary Pass Logic, Complementary CMOS, Transmission Gate, Transmission Function, 24 Transistor, 14 Transistor, 10 Transistor, Swing Restored Complementary Pass Logic, Hybrid Pass Static CMOS, Double Pass Transistor and some Hybrid full adder cells have been conducted using Cadence Virtuoso Tools in 90nm technology. It was observed that Complementary Pass Logic adder cell had the least delay and 14-Transistor adder cell displayed the worst delay. Hybrid Pass Static CMOS full adder had the least power consumption whereas 24 Transistor full adder consumed highest power. Highest power-delay product was displayed by Double Pass Transistor Logic adder cell.