Test Vector Reordering by using Hybrid Genetic Algorithm-Simulated Annealing for Lower Switching Activity

Test power dissipation is way higher than normal mode power dissipation due to extensive switching activity, which affects the reliability of the device. Switching activity can be reduced by reordering of test vectors without modification in the circuit under test. In this work, a genetic algorithm with simulated annealing is proposed for reordering of test patterns and thereby finding optimum orders of test vectors to reduce overall switching activity at the time of application of test vectors. Hamming distance among consecutive test patterns is minimized in this work for reordering the sequence. Experimental results demonstrate a significant improvement of 16.5% in the reduction of switching activity on ISCAS'89 benchmark circuits.