Performance Analysis of 10 nm FinFET with Scaled Fin-Dimension and Oxide Thickness

This research work presents the performance analysis of multi-gate FinFET structure simulated at 10-nm technology node. The device electrical parameters have been extracted at different Fin dimensions to analyze the effect of Fin-scaling and oxide thickness variation onto the device performances. The designed device has been simulated at different heights and widths of the Fin. Thereafter, the oxide thickness has been varied for the structure. The effects of Fin height, width, and oxide thickness variation have been reported. The minimum value of Drain Induced Barrier Lowering (DIBL) has been observed at H_fin of 27 nm with I_ON/I_OFF ratio as 1.89×10⁴ to 3.1×10⁴. The lowest Subthreshold Swing (SS) of 59.5 mV/decade is obtained at H_fin of 40 nm. At different Fin-width values, it has been observed that the DIBL reduces with the reduction in Fin-width but the drain current increases only with higher Fin-width and hence, ON current increases. This research work provides a better understanding to the scaling of the complex structure design of FinFETs.