Novel Approach to Design DPL-based Ternary Logic Circuits

Present paper introduces a novel strategy to design Double Pass-transistor Logic (DPL)based Ternary (base-3)logic circuit in favour of wave-pipelined applications. Ternary can be a feasible candidate to replace conventional binary (base-2)number system due to faster computation, reduced interconnect complexity, reduced fan-in/fan-out, less storage requirement and so on. Careful design with proper coarse and fine tuning of wave-pipelined circuit can improve the overall performance and reliability of digital SOC. DPL is a favourable candidate for wave-pipelining and is employed in this work. Ternary digit (“trit”)value “0”, “1” and “2” are coded with 0 V, 0.9 V and 1.8 V respectively. In order to validate proposed strategy the 2-input TXOR, TAND and TOR circuits are designed and the simulation results are verified. Speed-power performance of designed circuit is recorded. All the simulations are carried out on TSMC
$0.18\mu\mathrm{m}$
CMOS technology with 1.8 V supply rail and at 25°C temperature using Tanner EDA.V13.