Incorporation of Tensile and Compressive Channel Stress by Modulating SiGe Stressor Length in Embedded Source/Drain Si-FinFET Architecture

The effect of Silicon-Germanium (SiGe) volume in an embedded source and drain Si-FinFET device structure has been studied in this article. The study has been carried out thoroughly using the process and device technology computer-aided design (TCAD) simulator from Synopsys. A new technique for incorporating uniaxial tensile stress in the Silicon channel region has been introduced by fractionally SiGe embedded source/drain region in 3-dimensional FinFET architecture. It has been found that when the SiGe length in source/drain regions become equal to the length of gate region from channel-source/drain interface induce maximum tensile stress of 274 MPa in the silicon channel which improves the performance of n-type Field Effect Transistor (FET) devices. However, fully SiGe embedded source/drain region induce conventional compressive channel stress of 513 MPa which helps to increase different performance parameters of p-channel devices. Thus, for the first time, it has been reported that by controlling the stressor length/volume, both tensile and compressive strain can be introduced in the channel of a Si-FinFET device structure. The channel, source/drain, and stressor regions have been observed to control the overall nature and amount of incorporated stress and thus the proposed design is capable of improving the performance of both p-type and n-type FinFETs without any fabrication overhead.