Low Memory Architectures of Fractional Wavelet Filter for Low-Cost Visual Sensors and Wearable Devices

This paper proposes a low memory architecture of fractional wavelet filter for computing two-dimensional discrete wavelet transform of gray-scale images. The proposed architecture uses a data scanning order which mainly contributes to memory reduction. A multiplierless version of the proposed architecture is also designed to reduce the critical path delay equal to the delay of an adder. The proposed architectures and an existing low memory discrete wavelet transform architecture are implemented on the same field programmable gate array board and their performance are compared for different image resolutions. The results show that the proposed architectures (with and without multipliers) uses lesser basic blocks, such as look-up tables (about 85-94% less), flip-flops (about 85-90% less), consumes lesser dynamic power (about 58-75% less), and results in critical path delay reduction of (about 23-77%) compared to one of the best existing low memory discrete wavelet transform architecture for images of $1024\times {1024}$ pixels. These advantages are achieved in addition to reduction in memory requirement over the existing state-of-the-art architectures. Thus, the proposed architectures are viable options for calculating discrete wavelet transform coefficients of gray-scale images on low-cost memory-constrained platforms like visual sensors/wearable devices and Internet of things.