FPGA Implementation of pAsynch Design Paradigm

Information leakage through physical channels is a major security vulnerability for embedded hardware. Power analysis is a well known technique used for side channel attacks. This paper overviews a new design paradigm, dubbed pAsynch, recently proposed by our group as an effective circuit level countermeasure against Power Analysis Attacks. pAsynch utilizes both the internal state and random signals to uniformly spread the information-carrying energy within the clock period. This paper is based on previous publications discussing pAsynch in detail and focuses on the practical implementation of pAsynch protection scheme on FPGA, overcoming some of the inherent challenges associated with the clocking scheme that is the basis of this technique. We show that pAsynch can provide h/w security with low overhead, making it suitable for energy/area constrained applications.