Phase Disposition Modulation With Sorting Algorithm for Symmetrical Cascaded Multilevel Converters

This paper proposes a new carrier-based modulation strategy for symmetrical cascaded multilevel converters denominated phase disposition with sorting (PDS). It deals with the issue of irregular distribution of PWM signals and power for each converter cell that occurs when using the conventional phase disposition (PD) modulation. Although some alternatives have been proposed in the literature for overcoming these problems, most of them do not consider operation of the converter under fault conditions on the power cells. Therefore, one of the contributions of the proposed PDS modulation strategy is the ability to evenly distribute the pulse signals for the converter semiconductor switches, resulting in the same power being processed by all cells, maintaining the good quality of the synthesized output voltages, even with faults in one or more power cells. In addition, it allows implementation in commercial digital signal processors, not requiring additional hardware. The good performance of the proposed modulation strategy is validated through experimental results for a three-phase symmetrical cascaded multilevel converter with three cells per phase, considering normal and faulty conditions on the power cells.