Limits to voltage scaling from the low power perspective

Scaling the power supply voltage enables a quadratic reduction in dynamic power dissipation with a reduction in performance which can be partially compensated by scaling the threshold voltage. There are difficult manufacturing limitations when scaling threshold voltages (mainly due to intra- and inter-chip variations) but the general view seems to be that continuous voltage scaling would be beneficial if manufacturing allowed it. While these qualitative results are well-known, we present for the first time a quantitative analysis of voltage scaling limits from the low power perspective. Our main new result is that optimizing the supply and threshold voltages for minimum energy-delay product is independent of the process or technology (up to a first order analysis). With this theoretical analysis followed by extensive simulations, we show that, for a given circuit, the optimal supply and threshold voltages are approximately the same in all CMOS technologies available through MOSIS (2 /spl mu/m to 0.35 /spl mu/m). This result is nonintuitive, represents a clear limit to voltage scaling from the low power point of view, and is contrary to the common view of a continuously scaling scenario if technology permits. The limit is not absolute, though, since it can be overcome by circuit design techniques (e.g. reducing logic depth), or other techniques (e.g. cooling).