Online VHDL Generator and Analysis Tool

Development of digital systems with standard hardware description languages (HDL) is considered difficult to unexperienced designers due to complex modeling syntax and semantic rules. In the paper, we propose a novel HDL modeling methodology based on simple digital model description. We present an open online tool for model parsing, analysis and automatic translation to VHDL. The simplified language enables quick development of digital circuits and the tool outputs readable VHDL with test bench for back-end synthesis and simulation.