Improvement of Cell’s Performance for Low Power Self-Aligned Split-Gate SONOS Memory Device

A novel low power split-gate SONOS is proposed to improve cell’s performance. The self-aligned fabrication steps of this novel device are presented and the characteristic is demonstrated. It was found that electrical characteristics of this novel split-gate SONOS device are superior to that of the conventional one. The improvement of electrical characteristics is mainly ascribed to the absence of counter-doped channel in the selected gate (SG) or memory gate (MG) transistor, which is inevitable in those conventional low power split-gate SONOS devices. The absence of counter-doped channel is achieved by using source-side self-aligned halo implant for VTH adjustment of SG transistor. Degradation of mobility due to counter-doped channel can be avoided. Consequently, higher on-state current can be acquired. Additionally, proposed split-gate SONOS device exhibits independence between the VTH,SG and VTH,MG, which brings better reliability.