On-Resistance Improvement Impacted by Trapping Effects in Fin-LDMOS Technology

An interface trapping model of shadow trench isolation (STI)/fin boundary for a laterally diffused metal oxide semiconductor (LDMOS) is proposed, and trapping effects on on-resistance (Ron) is comprehensively studied in 14-nm FinFET technology. In this paper, the dependencies of thermal treatment splits after STI deposition on Ron are also investigated. It is shown that Ron is reduced 80% for p-type LDMOS, and increased 20% for n-type LDMOS with increase of thermal treatment temperature, which indicts thermal treatment process of STI has a contrary effect on Ron variation. The different well doping conditions of drift region are also investigated to further understand the trapping model of STI/fin. Three groups of devices including high, median, and low dose/energy are designed to verify the interface trapping model of STI/fin boundary. With increase of implanting concentration and energy, there are 70% and 10% Ron reduction for both p-type and n-type LDMOS respectively. It implies that high dose and energy are conductive to improve Ron of Fin-LDMOS in 14-nm FinFET technology. The presented TCAD simulation results are consistent with our experimental results.