Geometry Optimization of Current-Mode Full Symmetric Vertical Hall Device by TCAD Simulation

This paper introduces a current-mode low-offset and high-sensitivity full symmetric vertical Hall device (FSVHD). The effect of device geometry structure and contact size on sensitivity and offset was studied by TCAD simulation. Based on current-mode, the structure of FSVHD was optimized to achieve both high sensitivity and low offset in 0.18-μm standard CMOS technology. TCAD simulation reveals that the sensitivity in the current-mode is twice larger than that in the voltage-mode. Further, the current-mode sensitivity is increased from 1.8% T⁻¹ to 2.4% T⁻¹ and the offset is reduced by an order of magnitude by optimizing the structural parameters.