Inverter-Based Fast Transient Response Capacitor-Less LDO

This paper proposes a fully integrated low dropout regulator (LDO) with fast transient response capability without the need of external off-chip capacitors. Based on the traditional LDO, two inverters are inserted between the gate of the PMOS and the output stage of the error amplifier. At steady state of LDO, the inverter increases the line and load regulation because it acts as a gain stage. At transient state, the inverter provides a fast transient discharge or charge path to the gate of the PMOS transistor. Fast charging and discharging greatly increase the slew rate of the gate, thereby effectively reducing overshoot and undershoot during transient. The proposed LDO is designed by TSMC 65-nm standard CMOS process. The quiescent current of the LDO is 10 uA, and the line and load regulation are 1 mV/V and 0.6 $\mu$V/mA, respectively. For an input voltage of 0.7V and an output voltage of 0.5 V, the voltage spike and the recovery time are reduced to 17 mV and 109 ns, respectively, whereas they are more than 250 mV and 5 us for the conventional structure.