Achieving Secure, Reliable, and Sustainable Next Generation Computing Memories

The design of next generation memory systems for increasingly large datasets is primarily being pursued through two fronts: (1) The continued progression of process scaling for conventional memories such as DRAM and Flash and (2) the commercialization of emerging non-volatile memory technologies including Phase Change, Resistive, and Spin-Torque Transfer Magnetic memories. Both avenues have illuminated reliability concerns including crosstalk-based disturbance and limited endurance. Crosscutting to these issues are challenges in maintaining or improving performance and operational energy. However, an emerging critical challenge is understanding, quantifying, and optimizing the sustainability of these memories in the face of exponentially increasing embodied costs (including energy and carbon emissions) due to the fabrication approaches of increasingly smaller nodes and processes for new technologies.I have contributed several approaches to different layers of this effort. For example, I designed low-energy network-on-chip (NoC) buffers for many-core systems using domain-wall memories. To support fault tolerance in these memory technologies, I have designed several fault map approaches. Based on knowledge of the types of faults in particular memory technologies and in using these fault maps, I have designed low-overhead encoding schemes to avoid faults and developed methods to increase memory lifetime. I have also developed collaboratively designed approaches that integrate fault tolerance with security. Finally, I have demonstrated the energy and environmental impacts of different memory design choices including technologies and fault tolerance approaches with holistic energy tradeoff analyses. My work provides advances in architectures, fault tolerance, security, and sustainability of these next generation memory systems.