Multi-Voltage Domain Power Distribution Network for Optimized Ultra-Low Voltage Clock Delivery

In this paper, the co-design of the clock and power delivery networks is proposed for ultra-low power IoT applications operating in sub-threshold. A distributed, multi-voltage domain and hierarchical power distribution network is proposed to deliver current to the clock buffers, registers, and combinational circuits in local clock distribution networks. The variation of the clock skew, setup time, hold time, and clock-to-q delay are analyzed under process and supply voltage variation. The effect on timing due to supply and process variation is analyzed for a target operating voltage and frequency of, respectively, 250 mV and 2 MHz in a 130 nm CMOS technology. The minimum clock period, skew, and insertion delay are reduced to, respectively, 0.74×, 0.52×, and 0.79× when optimized sub-threshold buffers are implemented, as compared and normalized to a clock network that includes non-optimized buffers. In addition, the co-designed clock and power networks were resilient to as much as 10% variation in the supply voltage when the proposed multi-voltage domain and distributed power distribution network is used with the optimized clock buffers.