Area–Time–Power Efficient FFT Architectures Based on Binary-Signed-Digit CORDIC

Fast Fourier transform (FFT) is a significant technique in the digital signal processing (DSP). The intrinsic weak point of the primary designs of FFT was the use of multipliers. CORDIC is the most prevalent method to replace the multipliers of FFTs. In order to enhance the speed of CORDIC, redundant binary signed-digit (BSD) encodings can be utilized, so-called BSD-CORDIC. The main goal of this paper is to improve the efficiency of BSD-CORDIC-based FFT. The redundant improved composed (RIC) CORDIC is proposed as a novel BSD-CORDIC. The main idea behind the RIC CORDIC lies in prior determination of the required iterations in such a way that the maximum number of iterations is reduced, which results in speedup and decrease in hardware resources. Also, some of the iterations still can be skipped, which leads to further reduction in the power consumption. The synthesis results demonstrate that the FFT based on the RIC BSD-CORDIC enhances speed, power consumption, and area overhead.