Circuit Model for Statistical Method Based Reliability Estimation of MOS Transistors and Analog CMOS Circuits

Modern CMOS technologies are continuously scaling down. As a result of this, analog designers have serious reliability problems in their designs caused by physical effects such as hot carrier injection, negative and positive bias temperature instability (N/PBTI) and temperature dependent dielectric breakdown (TDDB). Therefore, it is an important factor estimating the deviations caused by these degradation mechanisms for a robust design. Note that the reliability of CMOS structures are considered for more than 40 years. Several works have been performed on these degradation effects in MOS structures and appeared in the literature. In most of the reliability studies available in the literature, physical models were proposed. However, difficulties in preparation of physical models seem to be the most important disadvantages of these type models. To overcome these disadvantages of physical models, statistical methods based on observation of experimental results have been introduced in some works. In this talk, statistical methods for modelling of the degradation caused deviations in the drain current and threshold voltage of the N-MOS and PMOS transistors are reviewed. [Note that these models are based on the observations by operating the device under stress voltage conditions. Using these observation results the effect of degradation was investigated statistically and a new statistical method was introduced to be an alternative to those given in the literature. The observed and the estimated values of the degradation are compared. The models introduced are independent of the realization technology and exhibit short simulation time and high accuracy. All data in this review is taken from the recent research works performed in Istanbul University and Istanbul Technical University.