Design of a Low Power Dynamic Comparator in 180nm CMOS Technology

This paper aimed towards compact and low power dynamic CMOS comparator in 180nm technology with supply voltage of 1.8V. Comparator is proposed in this paper using circuit level techniques LECTOR, GALEOR, ONOFIC, LCNT & LCMT in which two leakage transistors are added between pull up and pull down network of logic circuit in different styles and are used to design circuit with no critical path. Approach of leakage transistor is to conceive a state with more than one transistor OFF in a trail from supply voltage to ground. It is significantly less leaky than a state with only one transistor OFF in trail of from supply to ground. Proposed comparator circuit performance analysis is done in respect of power dissipation and delay. Total power dissipation in conventional circuit is 67.027pW with delay 79.940ps. In LECTOR and GALEOR power consumption is in range of 50-60pW. In ONOFIC and LCNT power dissipated in the range of 40-45pW. In LCMT power reduces to 92% as compared to conventional comparator. Moreover, power delay product (PDP) results also have been compared for comparator circuit. Power consumption of comparator is also compared with earlier reported circuits and proposed circuit’s shows better performances.