A Radiation-Hardened 12-bit SAR ADC Design

Charge redistribution capacitance based Successive approximation register (SAR) is one of the most common topologies of analog-to-digital converters (ADCs). However, this topology is prone to radiation-induced errors, particularly Single Event Transient (SET). The consequences are erroneous output sequences oreven system crash. In this paper, we will propose a novel design of a 12-bit SAR ADC. Simulation results demonstrate that it features significantly higher tolerance to SET when compared to the reference design.