New improved Design for Low Leakage and high performance SRAM cell in ULP Applications

In present day electronic industry, the device size is day by day shrinking and memory is an integral part of present day battery operated and hand held electronic gadgets. So with the reduction in device size, memory is also scaled down and this increases the demand for low power devices. The utmost requirement is long battery for the devices capable of performing complex functions. Most of the devices use SRAM for cache memory and require low leakage in standby mode. This paper presents 6T SRAM designed using two fingers which shows reduction in leakage power. The simulations and layout are done on Cadence tool using UMC 55nm technology. It is shown that leakage current and delay can be improved by this technique.