Clocking for HPC Design: Challenges and Experience Sharing

In recent years, as the progress of VLSI technology, artificial intelligence / deep learning has become a major trend. To satisfy the demand of high performance computing, many AI ASICs adopt multi-core architecture. The challenges for clocking of this architecture consists of timing closure issues and the implementation of low latency, low skew and low OCV top-level clock tree for highspeed operation (> 1GHz). In this paper, we share our experiences on clock tree synthesis of HPC ASICs. Two different clocking strategies are introduced including H-tree planning with customized big drivers and clock mesh.