Design of an Adaptive and Reliable Network on Chip Router Architecture Using FPGA

We propose an adaptive, low cost, reliable and high performance router implemented based on a conventional two stage pipeline. The proposed Adaptive routing operates in adaptive mode as soon as the congestion is detected in network. We employ fault tolerant strategies for different components of routers such as input buffer, route compute unit, virtual channel allocation, switch allocation, and crossbar unit. The proposed router architecture differs from existing reliable routers, our implementation maintains the performance of fault tolerance router under massive network workloads by influencing the features of a crossbar, routing algorithm and router pipeline optimization. Our designed router is highly reliable than current fault receptive routers such as Wang[1], Vicis[2], BulletProof[3], RoCo[4] and Poluri[5]. The average latency is reduced by 0.69% and increased by 2.0% compared to fault tolerant and conventional router.