High-Performance NoC Simulation Acceleration Framework Employing the Xilinx DSP48E1 Blocks

An FPGA based Network on Chip (NoC) simulation acceleration framework is presented in this paper. The functionality of the crossbar switch of the NoC router is embedded in the hard multiplexers of the Xilinx DSP48E1 slices. A significant reduction in the soft logic (LUT+FF) utilization of the FPGA implementation of the 6 × 6 Torus topology has been observed by employing the hard multiplexers of the DSP48E1 slices in the proposed work. DSP based crossbar implementation of the 6 × 6 Torus topology consumes 38% fewer LUTs and 45% fewer FFs than the LUT based crossbar implementation. 35% less power consumption has been observed in the DSP based implementation. The proposed work utilizes 76% fewer LUTs compared to the state-of-the-art CONNECT NoC generation tool. Buffered, bi-directional Torus topology with XY routing has been considered in the proposed DSP based implementation compared to the Hoplite-DSP which implements the bufferless, unidirectional Torus topology with deflective routing algorithm. The proposed framework achieves the speed up of 2.02× and 2.9× with respect to the LUT only and the CONNECT NoCs.