A New Computing Paradigm Leveraging Interconnect Noise for Digital Electronics Under Extreme Environments

Digital CMOS based Integrated Circuits are susceptible to both permanent and transient errors in extreme environments like space due to radiation. The vulnerabilities arise mostly due to the static CMOS circuit style and use of planar devices, which can have junction breakdowns and latchups under radiation. These effects are expected to worsen with technology scaling. We propose a new computing fabric that not only provides a scalable alternative to traditional CMOS but also incorporates intrinsic fabric features for radiation resilience. A core component of the fabric is metallic nano-lines organized compactly. Whenever signal transitions take place in these metal lines, the sum of their crosstalk interference gets induced through virtual coupling capacitance in another metal line that was left floating (not connected to any signal/VDD/GND); in this case the transitioning signals are inputs and the net induced charge on the floating metal line is the output. Coupling strength between the input and output nano-lines and the net induced charge determines the logic being computed. The Crosstalk Computing fabric requires very few devices, which also implies less susceptibility. A byproduct of using interference for computing as opposed to device switching dependency is that whenever a high current spike is induced on interconnects due to radiation, the charges will get shared in multiple coupling capacitances connected to the net and thereby prevent extra charge build up at device nodes. Besides, the circuit style is dynamic as opposed to static CMOS, which also decreases the window of vulnerability. Moreover, the devices used in this fabric are ultra-thin body SOI Junction-less nanowire transistors where CMOS like latch-up mechanism is impossible as the substrate is not conductive. Our simulation results validate the concepts for radiation hardening and also indicate potentials for huge improvements; for a full adder design, density benefit is over 5x. Under worse case radiation scenarios, the simulations show superior resilience compared to CMOS.