Design of Digital Lock-in Amplifier Based on DSP Builder

In order to improve the performance of the digital lock-in amplifier and reduce the logic resources occupied in hardware, this paper designs a modular design scheme based on DSP Builder, making the design of the digital lock-in amplifier intuitive and simplified. This paper designs an internal excitation mode digital lock-in amplifier. After the simulation, the compiled program is downloaded to the FPGA device. The logic elements consumption rate is only 18%, reducing the resource usage of FPGA devices effectively. Experimental results show that the signal measurement error is less than 0.05% when the SNR of the measured signal is -14dB and the amplitude is greater than 500mV. Therefore, the digital lock-in amplifier can effectively detect weak signals.