Performance improvement and hardware implementation of Open Flow switch using FPGA

The architecture of current networks is static and nonprogrammable. In Software-Defined Networking (SDN) it is possible to have programmability and innovation within the network. In SDN, data plane and control plane are separated. So, the network operators can manage the network behavior using software. Some standardized interfaces such as OpenFlow are developed to enable the interaction among the controller and switches. OpenFlow switch manages the network traffic at the data plane. Packet parser is one of the main parts of OpenFlow switch. So far, some FPGA implementations have been presented for packet parsers for the SDN which lack required flexibility and programmability. These implementations support only one parse graph which causes limitations in creating new network protocols for new versions of the OpenFlow switch. To address this problem, in the present study the automatic generation of a programmable packet parser is presented for the OpenFlow switch. In addition to creating high flexibility in the switch, our proposed implementation is programmable and support different parse graph during the execution time. Simulation and implementation verify the appropriate performance of this programmable parser in OpenFlow Switch. Our implementation is able to improve the performance of the switch and enhance the flexibility of the data plane of SDN. The use of the programmable packet parser results in the increase in the switch speed, the reduction in wait time and service time, and the improvement in the Openflow switch performance.