A 2.8-mW Sub-Harmonic Injection-Locked Frequency Multiplier in 130-nm CMOS for 2.4-GHz WLAN Applications

A low-power ring-oscillator-based injection-locked frequency multiplier with a continuous frequency-tracking loop (FTL) that generates 2.4 GHz frequency is proposed. This clock multiplier is designed for wireless local area network (WLAN) applications. A low-power delay cell is used to enhance the efficiency of the system. The FTL is used for continuous calibration of the ring voltage-controlled oscillator (VCO) frequency drift across process, supply, and temperature variations. The proposed architecture is designed using 130-nm CMOS process. The integrated RMS-jitter achieved is 272 fsec in the range from 12 kHz to 20 MHz of the 2.4-GHz output signal with total power consumption of 2.8 mW.